Aspects of energy efficient LDPC decoders

Amador, Erick

Iterative decoding techniques for modern capacity-approaching codes are currently dominating the choices for forward error correction (FEC) in a plethora of applications. Turbo codes, proposed in 1993 [1], triggered the breakthrough in channel coding techniques as these codes approach the Shannon capacity limit. This was followed by the rediscovery of low-density parity-check (LDPC) codes in the 1990s, originally proposed by Gallager [2]
in 1963. These codes are presently ubiquitous in the context of mobile wireless communications among other application domains.
In this dissertation, we focus on the aspects and challenges for conceiving energy efficient VLSI decoders aimed at mobile wireless applications. These nomadic devices are typically battery-operated and demand high energy efficiency along with high throughput performance on the smallest possible footprint. Moreover, these iterative decoders are typically one of the most power intensive components in the baseband processing chain of a wireless receiver.
We address the aspects for designing energy efficient LDPC decoders. At the algorithmic level we investigate the tradeoff among error-correction performance, energy efficiency and implementation area for different choices of message computation kernels. We identify the opportunities for energy savings that are enabled by the Self-Corrected Min-Sum (SCMS) kernel at three different levels: convergence speed, reduction on the number of active
nodes and an efficient stopping criterion. At this level we also propose a technique to evaluate the syndrome of the code in on-the-fly fashion that offers a speedup on the decoding task.
At the architectural level we focus on the memory subsystem design of an LDPC decoder since this module is responsible for the majority of the implementation area and power consumption. We propose a methodology for data partitioning and allocation within a flexible memory subsystem that in order to resolve conflicts. With the results from our studies at both
the algorithmic and architectural levels we present the implementation of a multi-mode decoder for the quasi-cyclic LDPC codes defined in IEEE 802.11n/16e.
At the system level we propose dynamic power management strategies that rely upon iteration control and workload prediction. For iteration control we propose a control law that is aided by two decision metrics that follow the dynamics of the decoding task. Regarding workload prediction, we propose a control law that adjusts online a power manageable iterative decoder that guarantees a task deadline while minimizing energy expenditure.

Systèmes de Communication
Eurecom Ref:
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