ICWMC 2010, 6th IEEE International Conference on Wireless and Mobile Communications, September 20-25, 2010, Valencia, Spain
Modern VLSI decoders for low-density parity-check (LDPC) codes require high throughput performance while achieving high energy efficiency on the smallest possible footprint. In this paper we present a valuable optimization to the processing step known as syndrome check. After each decoding iteration the updated posterior values are used to verify the validity of the codeblock and halt the decoding task. We partition this task and perform it on-the-fly in order to speed up the total task latency and eliminate hardware components. We present results for applying this technique to an LDPC decoder for the IEEE 802.11n standard.
Type:
Conférence
City:
Valencia
Date:
2010-09-20
Department:
Systèmes de Communication
Eurecom Ref:
3165
Copyright:
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