Receiver structures that have been proposed for the WCDMA downlink comprise chip level channel equalizers to restore code orthogonality and symbol level Linear Minimum Mean Square Error (LMMSE) receivers that furthermore exploit subspace structure in the signal due to unused codes. In this paper we focus on receivers for high-speed downlink communications. The combined transmission system, comprising spreading and channel ltering, is time-varying at chip rate in WCDMA systems, which makes LMMSE receivers necessarily highly time-varying. We consider the case of multi-code highrate communications (HSDPA) where inter-chip and inter-code interference dominate. We discuss optimization issues appearing in the advantageous combination of chip-level and iterative symbol-level equalization. Furthermore, iterative symbol-level operations allow for a continuous operation between linear and non-linear receivers.
Optimization issues in combined chip and symbol level equalization for downlink WCDMA receivers
Asilomar 2004, 38th IEEE Annual Asilomar Conference on Signals, Systems and Computers, November 7-10, 2004, Pacific Grove, USA
Type:
Conférence
City:
Pacific Grove
Date:
2004-11-07
Department:
Systèmes de Communication
Eurecom Ref:
1581
Copyright:
© 2004 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
See also:
PERMALINK : https://www.eurecom.fr/publication/1581
