SYCLARA: An open hardware-software platform for evaluating SYCL applications on RISC-V Vector accelerators

Over the past few years, two standards have gained significant momentum spurred by the growing interest in the design and development of customized, domain-specific hardware accelerators for AI and data analytics. On the hardware side, RISC-V has emerged as an open and extensible architecture with flexible vector extensions (RVV) for scaling computationally-intensive workloads. On the software side, SYCL has emerged as a standardized, cross-architecture programming model that can provide performance portability across several accelerators. In this work, we describe our efforts to bring these two standards together by (i) developing an FPGA-based hardware acceleration platform that integrates CVA6 RISC-V core with the ARA2 RVV implementation, and (ii) customizing the platform to enable SYCL kernel offload via the oneAPI Construction Kit. We evaluate several SYCL applications using this platform to demonstrate the benefit of RVV and make our platform publicly available as a standards-based testbed for evaluating SYCL applications on RISC-V vector accelerators.