The equaliser (11) includes a forward probability calculation circuit (13) which is connected at the input of a buffer register (17). A reverse probability calculation circuit (14) is also included. A working memory connected at the output of the forward calculation circuit memorises the probabilities. A combinational logic circuit (15) is connected at an input of the working memory (18a) and at the output of the reverse calculation circuit. This allows a value representing the probability of a symbol being transmitted over the channel (5) to be calculated.
Digital equaliser e.g. for mobile digital telephone
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