This course provides an overview of software and hardware design for smart objects. It shows how to specify, design and validate digital hardware components, how to integrate them in a microprocessor-based system, and how to drive them from the software layers.
Teaching and Learning Methods: Lectures, team-work, lab sessions. Students are provided with prototyping boards and design tools for the whole semester duration.
Course Policies: Attendance to the lab sessions is mandatory
Book: S. Kilts, "Advanced FPGA design: architecture, implementation, and optimization", IEEE Computer Society Press
Book: Peter J. Ashenden, "Designer's guide to VHDL", Morgan Kaufmann
Book: P. Simpson, "La conception de systèmes avec FPGA" (French), Dunod
Book: R. Zurawski, "Embedded systems handbook", CRC Press
Online book: "The Zynq book" (http://www.zynqbook.com/)
Binary representations of integers (sign+magnitude and two's complement). Boolean logic, boolean operators. Basic C programming. Basic GNU/Linux command line interface. Git, markdown.
- Digital hardware design, hardware description languages, simulation, formal verification, logic synthesis.
- Field Programmable Gate Array (FPGA) circuits, Systems-on-a-Chip embedding FPGA fabrics and their use to design a complete hardware / software product prototype.
- System integration, interfaces between components of a digital system, software drivers of hardware peripherals, software applications using hardware peripherals
The main goal is to reach a sufficient level of understanding to design alone a prototype system embedding one or several hardware operators for the processing and a micro-processor, plus its peripherals, for the control. A hands-on approach is taken, with the aid of state-of-the-art laboratory equipment.Most of the course is dedicated to the design of a hardware / software system on a prototyping board embedding a microprocessor and a FPGA matrix including dedicated digital hardware accelerators, their interfaces with the microprocessor, Linux drivers, software libraries and software applications to manage the hardware accelerators from the software stack.
Nb hours: 42.00, one introductory session (1.5h lecture + 1.5h team work), 6 mixed sessions (1.5h lecture + 1.5h lab) and 7 project lab sessions (1h guided work + 2h work on project)
Grading Policy: 50% project (about half of the labs are dedicated to a project), 50% written exam.