Ecole d'ingénieur et centre de recherche en Sciences du numérique

Access-time aware cache algorithms

Neglia, Giovanni; Carra, Damiano; Feng, Mingdong; Janardhan, Vaishnav; Michiardi, Pietro; Tsigkari, Dimitra

Research Report RR-8886, March 2016

Most of the caching algorithms are oblivious to requests’ timescale, but caching systems are capacity constrained and, in practical cases, the hit rate may be limited by the cache’s impossibility to serve requests fast enough. In particular the hard-disk access time can be the key factor capping cache performances. In this paper, we present a new cache replacement policy that takes advantage of a hierarchical caching architecture, and in particular of access-time difference between memory and disk. Our policy is optimal when requests follow the independent reference model, and significantly reduces the hard-disk load, as shown also by our realistic, trace-driven evaluation.

Document Hal Bibtex

Titre:Access-time aware cache algorithms
Département:Data Science
Eurecom ref:5065
Copyright: © INRIA. Personal use of this material is permitted. The definitive version of this paper was published in Research Report RR-8886, March 2016 and is available at :
Bibtex: @techreport{EURECOM+5065, year = {2016}, title = {{A}ccess-time aware cache algorithms}, author = {{N}eglia, {G}iovanni and {C}arra, {D}amiano and {F}eng, {M}ingdong and {J}anardhan, {V}aishnav and {M}ichiardi, {P}ietro and {T}sigkari, {D}imitra}, number = {EURECOM+5065}, month = {03}, institution = {Eurecom}, url = {},, }
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