Graduate School and Research Center in Digital Sciences

SoC security evaluation: Reflections on methodology and tooling

Corteggiani, Nassim; Camurati, Giovanni; Muench, Marius; Poeplau, Sebastian; Francillon, Aurélien

Invited paper in IEEE Design & Test, 2020

The growing complexity of Systems-on-Chip challenges our ability to ensure their correct operation, on which we rely for more and more sensitive activities. Many security vulnerabilities appear in subtle and unexpected ways in the interaction among blocks and across layers, where current verification tools fail at catching them or do not scale. For this reason, security evaluation still heavily relies on manual review. Inspired by the Hack@DAC19 contest, we present our reflections on this topic from a software and system security perspective. We outline an approach that extends the dynamic analysis of firmware to the hardware.

Document Bibtex

Title:SoC security evaluation: Reflections on methodology and tooling
Keywords:Security evaluation, System-on-Chip, dynamic analysis, HardFails
Type:Invited Journal
Language:English
City:
Date:
Department:Digital Security
Eurecom ref:6307
Copyright: © 2020 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Bibtex: @article{EURECOM+6307, year = {2020}, month = {07}, title = {{S}o{C} security evaluation: {R}eflections on methodology and tooling}, author = {{C}orteggiani, {N}assim and {C}amurati, {G}iovanni and {M}uench, {M}arius and {P}oeplau, {S}ebastian and {F}rancillon, {A}ur{\'e}lien}, journal = {{I}nvited paper in {IEEE} {D}esign \& {T}est, 2020}, url = {http://www.eurecom.fr/publication/6307} }
See also: