Hardware optimized sample rate conversion for software defined radio
FREQUENZ, Journal of RF-Engineering and Telecommunications, November-December 2010, Vol 64, N°11-12
The evolution towards applications with increasing functionalities leads to the need of high flexible systems that support a high number of different standards while decreasing the required hardware space. Therefore a high configurable platform being able to handle a multitude of standards is needed. One main issue is the tradeoff between performance and space consumption. We present a generic, flexible, fractional and hardware optimized SRC architecture in the context of SDR, providing one architecture to process up to 8 different complex channels. The solution is based on bandlimited interpolation and allows processing by supporting a 1Hz resolution of the sampling rates.
| Keywords: | SDR, SRC, Hardware Architecture, Open Platforms for Multistandard Support, Baseband |
| Type: | Journal |
| Language: | English |
| Date: | December 2010 |
| Department: | Mobile Communications |
| Eurecom ref: | 3302 |
| Copyright: | Schiele & Schön |
| Bibtex: | @article{EURECOM+3302, doi = {http://dx.doi.org/10.1515/FREQ.2010.64.11-12.204}, year = {2010}, month = {12}, title = {{H}ardware optimized sample rate conversion for software defined radio}, author = {{S}chmidt-{K}norreck, {C}arina and {K}nopp, {R}aymond and {P}acalet, {R}enaud }, journal = {{FREQUENZ}, {J}ournal of {RF}-{E}ngineering and {T}elecommunications, {N}ovember-{D}ecember 2010, {V}ol 64, {N}°11-12}, url = {http://www.eurecom.fr/publication/3302} } |
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Permalink: http://www.eurecom.fr/publication/3302
